1. Field of the Invention
The present invention relates to a direct digital synthesizer for use in communication equipment, and more particularly to a direct digital synthesizer for supplying signals of a prescribed frequency in accordance with an entered reference clock and frequency data that are set.
2. Description of Related Art
A direct digital synthesizer (DDS) conventionally used in communication equipment is usually provided with a phase accumulator. This phase accumulator consists of an adder. This adder receives frequency data at one of its inputs and its own output at the other, adds them in synchronism with an external clock, and successively supplies the results of addition as the output of the phase accumulator.
The output value of this phase accumulator is entered into a phase-amplitude converter to be converted into amplitude data of DDS output signals. More specifically, many of such phase-amplitude converters convert the computation output of a phase accumulator into amplitude data of a sine waveform. Next, these amplitude data are converted by a D/A converter into analog signals to obtain DDS output signals.
In designing a DDS, first the frequency of a reference clock and the number of bits computed by the phase accumulator are determined according to the step of frequency required for the output signal.
Next, with this reference clock frequency being used as the sampling rate, the number of input bits for the D/A converter is determined according to the precision requirement of output signals, and the number of output bits for the phase-amplitude converter is determined to match the number of input bits for the D/A converter. Finally the number of bits to be entered into the phase-amplitude converter out of the computation result of the phase accumulator is determined.
Incidentally, D/A converters for use in a DDS are usually expensive. Therefore, a device with the minimum required number of input bits is selected.
On the other hand, the number of bits computable by the phase accumulator is determined by the frequency step required for output signals. For this reason, the smaller the output frequency step, the greater the number of bits required.
Accordingly, in many cases, the number of bits computable by the phase accumulator is substantially greater than the number of output bits of the phase-amplitude converter (equal to the number of input bits of the D/A converter). Therefore, the designer arranges his or her design so that only the more significant bits out of the computation result of the phase accumulator be entered into the phase-amplitude converter without entering some of the less significant bits, because entering a greater number of bits into the phase-amplitude converter, greater beyond a certain limit, than that of output bits would require an extremely large scale phase-amplitude converter, which inevitably is expensive.
On the other hand, the value represented by the less significant bits not entered into the phase-amplitude converter out of the computation result of the phase accumulator constitutes the rounding error of the input data for the phase-amplitude converter. However, as this rounding error is used every time the phase accumulator repeats its computation, a carry occurs on the more significant bits periodically.
Since input data for the phase-amplitude converter contain such carries, the sine waveform of DDS output signals suffers phase jumps at the frequency of carry occurrence, and spurious signals arise in the spectrum of DDS output signals. The occurrence of such spurious signals will be explained in more detail below. A spurious signal arises as a consequence of either one of the following two circumstances.
[1] A phase jump in an output signal resulting from periodic carries to more significant positions of the result of addition of less significant bits not entered into the phase-amplitude converter out of the output bits of the phase accumulator, and a spurious signal attributable to it:
For the sake of simplicity of explanation, the output of the phase accumulator is divided into more significant m bits and less significant n bits (m and n are natural numbers; the same applies hereinafter), m being 4 and n, also 4.
It is supposed that the more significant m bits are entered into the phase-amplitude converter, but the less significant n bits are not.
It is further supposed that both the more significant m and the less significant n bits be connected to one of the inputs of the phase accumulator, frequency set data S are entered into the other input, and the addition is repeated in accordance with a reference clock.
Further explanation will be given below with reference to specific actions.
The initial value P0 of the computation result of the phase accumulator is supposed to be:
P0=0000, 0000(B)xe2x80x83xe2x80x83(1)
xe2x80x9c(B)xe2x80x9d in Equation (1) indicates binary notation, and xe2x80x9c,xe2x80x9d represents the boundary between the more significant m and less significant n bits.
Now the frequency set data being represented by S1, the following being set:
S1=0100, 0000(B)xe2x80x83xe2x80x83(2)
and the result of four rounds of addition by the phase accumulator being represented by P1:
P1=0000, 0000(B)xe2x80x83xe2x80x83(3)
As the addition is further repeated, the phase accumulator repeats supplying the same computation result in periods of four rounds of addition each, and the DDS output signals then are stable signals, free from spurious signals.
However, if the frequency set data are represented by S2, the following is set:
S2=0100,0001(B)xe2x80x83xe2x80x83(4)
and the result of four rounds of addition by the phase accumulator is represented by P2:
P2=0000, 0100(B)xe2x80x83xe2x80x83(5)
As the more significant m bits of P2 here is 0000(B), the same value as P1 of (3) is entered into the phase-amplitude converter, but the less significant n bits involve a rounding error for 0100(B).
This rounding error, if the phase accumulator further repeats addition, gives rise to a carry to the more significant m bits in the 16th round. The addition result then being represented by P3:
P3=0001, 0000(B)xe2x80x83xe2x80x83(6)
will hold, the more significant m bits being different from P1. This invites a phase jump in the DDS output signals.
Since a carry from the less significant n bits to the more significant m bits occurs every 16th round of addition by the phase accumulator, the DSS output signals suffer a phase jump at the same frequency. This invites a spurious signal of a frequency corresponding to the interval of phase jumps in the spectrum of DDS output signals. The frequency fs of such spurious signals can be generally expressed in the following equation.
fs1={mod(S/2n)/2n}xc2x7fclockxe2x80x83xe2x80x83(7)
In the foregoing equation, mod(A/B) represents the remainder of the division of A by B.
[2] A phase jump in output signals attributable to the remainder at the time of an accumulator overflow, and a spurious signal attributable to it:
A DDS output signals suffers the occurrence of a phase jump and a spurious signal, besides where the circumstance of [1] described above arises, when remainders at the time of overflowing of the phase accumulator have built up to overflow the accumulator.
For instance, where the value of the frequency set data S is set to be:
S3=0100, 0111(B)xe2x80x83xe2x80x83(8)
if the addition is done four times, the accumulator will be overflowed. The value P4 of the accumulator then will be:
P4=0001, 1100(B)xe2x80x83xe2x80x83(9)
This remainder will build up, and eventually this accumulated value itself will overflow the accumulator.
For instance, the next overflow will arise when the eighth addition is done, the remainder P8 then having built up in the accumulator will be:
P8=0011, 1000(B)xe2x80x83xe2x80x83(10)
At the following 11th addition, the accumulator will be overflow ed. At this time, the accumulator will have a further remainder P11:
P11=0000, 1101(B)xe2x80x83xe2x80x83(11)
This remainder P11 will again be accumulated by the ensuing repetition of additions, and repeat periodic overflowing. This overflowing due to the accumulation of remainders at the time of overflowing will give rise to a phase jump in the DDS output signal and to a spurious signal of a corresponding frequency component.
The frequency fs2 of this spurious signal can be generally represented by the following equation:
fs2=[mod{2(m+n/S}/2(m+n)]xc2x7fclockxe2x80x83xe2x80x83(12)
Known techniques to suppress the above-described two kinds of spurious signals include, for instance, what is disclosed in the Japanese Published Patent No. Hei 7-63124. This example of prior art will be described with reference to FIG. 1. With reference to FIG. 1, a DDS 3 receives a clock signal S1 from a reference frequency oscillator 1 and frequency data S2 from a frequency data setting circuit 2, and enters them into a phase accumulator 31. The phase accumulator 31 supplies phase data, and more significant bits S31a are entered into a phase-amplitude converter 32A. The phase-amplitude converter 32A supplies sine wave amplitude data S32a correspondingly to the entered bits S31a. A digital-to-analog (D/A) converter 33A converts these sine wave amplitude data S32a into an analog signal in synchronism with a clock signal S1, and supplies a sine wave signal S33a. 
The more significant bits S31a of the phase data are also entered into another phase-amplitude converter 32B. The phase-amplitude converter 32B supplies cosine wave amplitude data S32b orthogonal to the sine amplitude data S32a correspondingly to the entered bits S31a. A D/A converter 33B converts these cosine wave amplitude data S32a into an analog signal in synchronism with the clock signal S1, and supplies a cosine wave signal S33b. 
Out of the output of the phase accumulator 31, the less significant bits S31b, without the more significant bits S31a, are supplied to a D/A converter 33C. This D/A converter 33C subjects the value of less significant bits S31b to digital-to-analog conversion, and supplies a phase error signal S34. A multiplier 34 multiplies the cosine wave signal S33b by the phase error signal S34 to supply a spurious canceling signal S35. Then the subtractor 35 subtracts the spurious signal canceling signal S35 from the sine wave signal S33a, and supplies a spurious signal-free sine wave signal S3, which the DDS 3 aims at.
However, the technique disclosed in the above-cited patent, because it involves the combination of a precision arithmetic unit to perform computation for synthesizing a waveform, entails a disadvantage of complex structure.
It also involves another disadvantage of having three D/A converters, resulting in a high cost.
Its further disadvantage is the large number of adjusting steps, necessitated by the coordination of signal levels between the multiplier and the subtractor, in addition to the analog signal output level of each D/A converter, entailing complex work and a high adjusting cost.
An object of the present invention is to provide a DDS capable of suppressing phase jumps which would invite the generation of spurious signals, be more simply structured and permit ready adjustment.
A direct digital synthesizer according to one aspect of the invention is provided with a phase accumulator for generating phase data according to a reference clock and frequency data that are entered, and a variable delay circuit for delaying an output signal resulting from phase-amplitude conversion so as to compensate for any phase jump of the output signal according to the value of any rounding error arising at the time of subjecting the phase data to the phase-amplitude conversion.
A direct digital synthesizer according to another aspect of the invention is provided with a phase accumulator for generating phase data according to a reference clock and frequency data that are entered; a phase-amplitude converter for converting more significant m bits (m is a natural number) of the phase data supplied by the phase accumulator into an amplitude value; and a variable delay circuit for delaying the output signal of the phase-amplitude converter according to a phase compensation quantity obtained from the value of less significant bits of the frequency data, without the more significant m bits, and the frequency data.
A direct digital synthesizer according to one aspect of the invention compensates for any phase jump by controlling the variable delay circuit according to the value of any rounding error arising at the time of phase computation out of the output of the phase accumulator thereby to delay the output signal.